1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus, and in particular to a switching circuit, a tri-state circuit, a precharge circuit, a bus discharge circuit, a static bus system and a data processing apparatus, each of which comprises a bipolar transistor and a CMOS transistor.
2. Description of the Related Art
Hitherto, circuits comprising CMOS transistors have been widely used as static and dynamic bus drive circuits. In recent years, higher integration and higher performance of logic LSIs including microprocessors are demanded. With the advance of higher integration, the load of a bus drive circuit becomes heavy. On the other hand, a CMOS circuit has a drawback that its high-speed operation is obstructed by higher integration because its load drive capability is weak. This drawback is effectively overcome by using a BiCMOS bus driver comprising a MOS transistor at its input stage and a bipolar transistor at its output stage. However, bipolar transistors have problems such as the lowering of the current gain h.sub.FE due to the reverse voltage between the base and the emitter and occurrence of false base current caused by charge and discharge of parasitic capacitance associated with the base. Unless these problems are overcome, bipolar transistors cannot be activated at high speed.
FIG. 22 is a drawing for explaining the problem of reverse voltage between the base and the emitter. In FIG. 22, numeral 2201 denotes an NPN transistor having a collector connected to a power source V.sub.1, an emitter connected to a bus 2200, and a base connected to reference potential (such as the ground) via a resistor 2202. The NPN transistor 2201 is in the quiescent state. Numeral 2203 denotes a tri-state driver. When a control signal E is "0", the tri-state driver 2203 is in the quiescent state, i.e., its output is in the floating state. When the control signal E is "1", an input signal a is inverted and outputted onto the bus 2200. Assuming that the amplitude of the signal existing on the bus 2200 is 0 to 5 V, reverse voltage of 0 to 5 V is applied between the base and the emitter of the NPN transistor 2201 because the base potential is 0 V. It is known that the current gain h.sub.FE of a bipolar transistor gradually lowers if the bipolar transistor is subjected to stress of reverse voltage between the base and the emitter. Thus, this is an important problem which must be overcome to ensure reliability.
FIGS. 23A and 23B schematically show generation of a false base current of an NPN transistor in the quiescent state. In FIG. 23A, numeral 2301 denotes an NPN transistor having a collector connected to a power source V.sub.CC and an emitter providing an output. And C denotes parasitic capacitance existing between the power source V.sub.CC and the base of the transistor 2301. If the potential of the emitter changes as shown in FIG. 23B in the quiescent state with the base current I.sub.B =0, the base potential also changes similarly. Therefore, a false base current i.sub.b flows through the capacitance C, and it is amplified to produce a false collector current i.sub.c.
FIGS. 23C and 23D schematically show generation of a false base current of a PNP transistor in the quiescent state. A false base current i.sub.b flows through capacitance C in the same way as the case of NPN transistor. A false collector current i.sub.c produced by the false base current can be represented as ##EQU1## where .beta. is a current amplification factor.
Assuming now that ##EQU2## and .beta.=50, it follows that EQU i.sub.c =30.times.10.sup.-15 .times.5.times.10.sup.9 .times.50=7.5(mA).
It is thus known that a large collector current flows in spite of the quiescent state.
This false collector current causes a large increase in power dissipation, and in addition becomes a load of another acting bus driver, its speed performance being largely degraded.
A representative circuit having a quiescent state is a tri-state circuit comprising a CMOS circuit or a BiCMOS circuit. In the BiCMOS circuit, the above described problem in the quiescent state must be overcome.
As the prior art of a tri-state circuit comprising a BiCMOS circuit, a circuit shown in FIG. 6 of JP-A-61-270916 can be mentioned. In this circuit, the above described problem of false collector current is solved, but the problem of lowering of the current gain h.sub.FE caused by stress of base to emitter reverse voltage of an NPN transistor is not solved.
As another example of the prior art, circuits shown in FIGS. 1 to 8 of JP-A-61-116417 can be mentioned. In circuits shown in FIGS. 1 to 4 of this example, the problem of the base to emitter reverse voltage and the problem of the false collector current are not solved yet. In circuits shown in FIGS. 5 to 8, the problem of the false collector current is not solved yet.
A further example of the prior art is a BICMOS tri-state circuit shown in FIG. 1 of U.S. Pat. No. 4,703,203.
FIGS. 26A and 26B show equivalent circuits of this circuit in the active state and in the quiescent state, respectively. However, MOS transistors fixedly set at OFF condition in respective states are removed from FIGS. 26A and 26B. Further, MOS transistors fixedly set at ON condition are represented by resistors having element numbers.
FIG. 26A shows the equivalent circuit for the active state. At this time, this circuit functions as a general BICMOS inverter. When the input V.sub.D is a "1" level, the output V becomes a "0" level. When the input V.sub.D is the "0" level, the output V.sub.O becomes the "1" level.
A PMOS 27 and an NMOS 28 represented for convenience by resistors 27 and 28 are provided to raise the output potential of "1" level to power source potential V.sub.DD and lower the output potential of "0" level to reference voltage V.sub.SS.
FIG. 26B shows the equivalent circuit in the quiescent state. At this time, the output of this circuit is disconnected from the power sources V.sub.DD and V.sub.SS, and the output V.sub.O is in the floating state. At this time, the base of the NPN transistor 8 is connected to the power source V.sub.SS via an NMOS 19 set at ON condition (and represented by a resistor 19). If the potential of the output V.sub.O is changed by the output of another tri-state circuit, therefore, the junction between the base and the emitter of the NPN transistor 8 is subjected to stress of reverse voltage. As a result, the NPN transistor 8 causes a failure or significant performance degradation incurred from the lowering in current gain h.sub.FE.
As heretofore described, the prior art has a drawback that both the demand for reliability and demand for performance cannot be satisfied because the problems relating to the essence of a bipolar transistor in the quiescent state is not solved.